The 1st ACM/IEEE International Symposium on

Networks-on-Chip

 

Technical Program

Click here for a pdf overview

 

All events will be held at Friend Center, Princeton University (click here for map). 

The nearest parking is located at Lot 21 which is connected to the venue by the Blue Line shuttle service (click here for shuttle map).

 

Sunday, May 6, 2007

 

10am-5pm         Tutorial: Networks on Chips

(Friend Center Convocation Room)

 

10-11:45am Network layer protocols and performance analysis

Axel Jantsch (KTH, Sweden)

 

11:45am-1:15pm     Lunch Break (Friend Center Convocation Room)

 

1:15-3:00pm Power, energy and reliability issues in NoC

Radu Marculescu (CMU)

 

3:00-3:15pm             Break (Friend Center Convocation Room)

 

3:15-5:00pm Tooling, OS services and middleware

Luca Benini (U. Bologna, Italy)

5:30pm - 6:30pm     Evening Reception (Prospect House)

Monday, May 7, 2007

 

8:00-8:30am             Breakfast (Friend Center Upper Atrium)

8:30-8:50am              Welcome address by General Chairs and Program Chairs (Friend Center Auditorium)

8:50-9:50am               Keynote 1:  William J. Dally, Stanford University,  "Enabling Technology for On-Chip Interconnection Networks" (slides)

(Friend Center Auditorium)

9:50-10:20am            Break

10:20am-12pm         Session 1: NoC design case studies

Session Chair: Matthias Blumrich, IBM Research

(Friend Center Auditorium)

 

Implementation and Evaluation of a Dynamically Routed Processor Operand Network (slides)

Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert McDonald, Stephen Keckler and Doug Burger (U. Texas at Austin)

 

On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus (slides)

Thomas Ainsworth (Northrop Grumman) and Timothy Pinkston (USC)

 

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC (slides)

Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee and Hoi-Jun Yoo (KAIST, Korea)

 

Architecture of the Scalable Communications Core

Jeffrey Hoffman, David Arditti Ilitzky, Anthony Chun and Aliaksei Chapyzhenka (Intel Corp.) (slides)

12-1pm                     Lunch Break (Friend Center Convocation Room)

1-2pm                      Marketplace: Showcase of chip prototypes and tool demos

Organizer: John Bainbridge, Silistix

(Friend Center Downstairs Atrium)

Tool name: Cosi NoC: Open Source Infrastructure for NoC Synthesis
Alessandro Pinto (Berkeley), Luca P. Carloni (Columbia), Alberto Sangiovanni-Vincentelli (Berkeley)

Chip name: NoCPro: FPGA-based NoC prototype
Umit Y. Ogras, Radu Marculesu (CMU)

Tool name: VeriNoC: Unified tool for NoC analysis and simulation
Umit Y. Ogras, Radu Marculesu (CMU)

Chip name: Dynamic voltage scalable opto-electronic transceiver front-end design
Xuning Chen (Princeton), Gu-Yeon Wei (Harvard) and Li-Shiuan Peh (Princeton)

Tool name: QNoC Simulator: Cycle-accurate system simulations and architectural exploration
Evgeny Bolotin, Zigi Walter, Avinoam Kolodny, Israel Cidon (Technion)

Tool name: Faust NoC platform
Romain Lemaire, Pascal Vivet (CEA-LETI)

Tool name: Demo of verification environment of "A Generic Model for Formally verifying NoC communication architectures"
Laurence Pierre (IMAG)

Chip name: DSPIN NoC: GALS-suited synthesizable NoC with no custom blocks
Ivan Miro-Panades (ST)

Tool name: Konark: Custom NoC Synthesis Tool
Glenn Leary (ASU), Krishnan Srinivasan (Sonics) and Karam S. Chatha (ASU)

Chip name: Scalable Communications Core (SCC)
Anthony Chun (Intel)

2-2:30pm                 Break (Friend Center Downstairs Atrium)

2:30-4:10pm         Session 2: Technology and circuit techniques

Session Chair: Jens Sparsoe, DTU, Denmark

(Friend Center Auditorium)

 

On the Design of a Photonic Network-on-Chip (slides)

Assaf Shacham, Keren Bergman and Luca P. Carloni (Columbia University)

 

NoC Communication Strategies using Time-to-Digital Conversion (slides)

Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment and Alex Yakovlev (Newcastle University, UK)

 

A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs

Shuming Chen and Xiangyuan Liu (NUDT, China)

 

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures (slides)

Ivan Miro Panades and Alain Greiner (UPMC, France)

4:10-4:30pm                Break (Friend Center Upper Atrium)

4:30-6:35pm         Session 3: System architecture, verification and  debug 

Session Chair: Partha Kundu, Intel

(Friend Center Auditorium)

 

Transaction-Based Communication-Centric Debug  (slides)

Kees Goossens, Bart Vermeulen (NXP), Remco van Steeden (U. Twente) and Martijn Bennebroek (Philips, NL)

 

The impact of higher communication layers on NoC supported MP-SoC (slides)

Theodore Marescaux, Erik Brockmeyer (IMEC) and Henk Corporaal (TU Eindhoven, NL)

 

The Power of Priority: NoC based Distributed Cache Coherency (slides)

Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar and Avinoam Kolodny (Technion, Israel)

 

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study (slides)

Dominique Borrione, Amr Helmy, Laurence Pierre (TIMA, France) and Julien Schmaltz (Saarland University, Germany)

 

Access Regulation to Hot-Modules in Wormhole NoCs (slides)

Isask'har Walter, Israel Cidon, Ran Ginosar and Avinoam Kolodny (Technion, Israel)

 

 

 

Tuesday, May 8, 2007

 

8:00-8:30am             Breakfast (Friend Center Upper Atrium)

 

8:30-9:30am              Keynote 2:  Giovanni De Micheli, EPFL, "Design Technologies for Networks on Chips" (slides)

(Friend Center Auditorium)

9:30-10am                 Break

10am-12:05pm         Session 4: Routing and Topology

Session Chair: Chita Das, Penn State University

(Friend Center Auditorium)

 

Approaching Ideal NoC Latency with Pre-Configured Routes (slides)

George Michelogiannakis, Dionisios Pnevmatikatos and Manolis Katevenis (ICS-FORTH, Crete, Greece)

 

A Power and Energy Exploration of Network-on-Chip Architectures (slides)

Arnab Banerjee, Robert Mullins and Simon Moore (Cambridge, UK)

 

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing (slides)

Terrence S.T. Mak, Pete Sedcole, Peter Y.K. Cheung, Wayne Luk (Imperial College, UK) and Kai-Pui Lam (TCU, Hong Kong)

 

Region-Based Routing. An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips (slides)

Jose Flich, Andres Mejia, Pedro Lopez and Jose Duato (UPV, Spain)

 

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing (slides)

Stephan Bourduas and Zeljlko Zilic (McGill U., Canada)

12:05-1pm                Lunch Break (Kalluri Corner)

1-2pm                       Panel Session  (Friend Center Auditorium)

Proliferating the Use and Acceptance of NoC Benchmark Standards

Organizer:    Axel Jantsch (KTH, Sweden)                                 

Moderator:   Ian Mackintosh (OCP-IP) (slides)                                              

Panelists:    John Bainbridge (Silistix) (slides)

                    Radu Marculescu (CMU) (slides)

                   Timothy Pinkston (USC and NSF) (slides)

                   Drew Wingard (Sonics) (slides)

 

Poster Session

Session Chair: Li Shang, Queen's University

2:00-2:30pm Poster presentations (Friend Center Auditorium)

2:30-3:30pm Posters + Refreshments (Friend Center Downstairs Atrium)

 

An analytical approach for dimensioning mixed traffic networks (slides)

Per Badlund and Axel Jantsch (KTH, Sweden)

 

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip (slides)

Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand (CEA-LETI), Vincent Beroulle and Chantal Robach (INPG-LCIS, France)

 

A study of NoC Exit Strategies (slides)

Mikael Millberg and Axel Jantsch (KTH, Sweden)


QNoC Asynchronous Router with Dynamic Virtual Channel Allocation (slides)

Rostislav Dobkin, Ran Ginosar and Israel Cidon (Technion, Israel)

 

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links (slides)

Simon Ogg (U. Southampton, UK), Enrico Valli (U. Bologna, Italy), Crescenzo D'Alessandro, Alex Yakovlev, Bashir Al-Hashimi (U. Newcastle) and Luca Benini (U. Bologna, Itlay)

 

Thermal Impacts on NoC Interconnects (slides)

Sheng Xu, Ibis Benito and Wayne Burleson (U. Massachusetts)


3:30-5:10pm               Session 5: Reconfigurable NoCs

Session Chair: Ran Ginosar, Technion

(Friend Center Auditorium)

 

NOC-centric security of reconfigurable SoC (slides)

Jean-Philippe Diguet, Guy Gogniat, Samuel Evain, Romain Vaslin and Emmanuel Juin (UBS/CNRS, France)

 

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases (slides)

Andreas Hansson (Eindhoven U., NL) and Kees Goossens (NXP, NL)

 

Mesh of Tree: Unifying mesh and MFPGA for better device performances (slides)

Zied Marrakchi, Hayder Mrabet, Christian Masson and Habib Mehrez (LIP6, France)

 

NoC-Based FPGA: Architecture and Routing (slides)

Roman Gindin, Israel Cidon and Idit Keidar (Technion, Israel)

7pm                        Dinner Banquet (Prospect House)

                               Dinner talk:  Reflections on 10 years as a commercial on-chip

                               interconnect provider (slides)

                               Drew Wingard, Sonics

 

                               NOCS 2008

                               Alex Yakovlev, Newcastle University, UK

 

Wednesday, May 9, 2007

 

8:00-8:30am             Breakfast (Friend Center Upper Atrium)

 

8:30-9:30am               Keynote 3:  Israel Cidon, Technion, "NoC: Network or Chip?" (slides)

(Friend Center Auditorium)

9:30-10am                   Break

10am-11:15am         Session 6: CAD and methodology for NoCs

Session Chair: Luca Carloni, Columbia University

(Friend Center Auditorium)

 

NoC Design and Implementation in 65nm Technology (slides)

Antonio Pullini (Torino), Federico Angiolini (Bologna), Paolo Meloni (Cagliari), David Atienza (EPFL), Srinivasan Murali (Stanford), Luigi Raffo (Cagliari), Giovanni De Micheli (EPFL) and Luca Benini (Bologna)

 

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance (slides)

Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee and Simon Moore (Cambridge, UK)

 

ASC, a SystemC extension for Modeling Asynchronous Systems, and its application to an Asynchronous NoC (slides)

Cedric Koch-Hofer, Marc Renaudin (TIMA), Vvain Thonnart and Pascal Vivet (CEA-LETI, France) 

11:15-11:45am            Break (Friend Center Upper Atrium)

11:45am-1pm              Session 7: NoC mapping and simulation

Session Chair: Riccardo Locatelli, STM, France

(Friend Center Auditorium)

 

Implementing DSP Algorithms with On-Chip Networks (slides)

Xiang Wu (AMD), Tamer Ragheb, Yehia Massoud (Rice U.) and Adnan Aziz (UT Austin)

 

A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network (slides)

Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien and An-Yeu (Andy) Wu (NTU, Taiwan)

 

Fast, Accurate and Detailed NoC Simulations (slides)

Pascal T. Wolkotte, Philip K.F. Holzenspies and Gerard J.M. Smit (U. Twente, NL)

 

1pm                               Closing


Home

Program

Hotel & Travel  Information

Call for papers (pdf)

Committees

Registration

Submission

TVLSI Special Section on NoCs (pdf)

DATE 2006 NoC workshop