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The 1st ACM/IEEE International Symposium on Networks-on-Chip
Technical Program Click here for a pdf overview
All events will be held at Friend Center, Princeton University (click here for map). The nearest parking is located at Lot 21 which is connected to the venue by the Blue Line shuttle service (click here for shuttle map).
10-11:45am Network layer protocols and performance analysis Axel Jantsch (KTH, Sweden)
11:45am-1:15pm Lunch Break (Friend Center Convocation Room)
1:15-3:00pm Power, energy and reliability issues in NoC Radu Marculescu (CMU)
3:00-3:15pm Break (Friend Center Convocation Room)
3:15-5:00pm Tooling, OS services and middleware Luca Benini (U. Bologna, Italy) 5:30pm - 6:30pm Evening Reception (Prospect House)
8:00-8:30am Breakfast (Friend Center Upper Atrium) 8:30-8:50am Welcome address by General Chairs and Program Chairs (Friend Center Auditorium)
9:50-10:20am Break
Implementation and Evaluation of a Dynamically Routed Processor Operand Network (slides) Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert McDonald, Stephen Keckler and Doug Burger (U. Texas at Austin)
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus (slides) Thomas Ainsworth (Northrop Grumman) and Timothy Pinkston (USC)
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC (slides) Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee and Hoi-Jun Yoo (KAIST, Korea)
Architecture of the Scalable Communications Core Jeffrey Hoffman, David Arditti Ilitzky, Anthony Chun and Aliaksei Chapyzhenka (Intel Corp.) (slides) 12-1pm Lunch Break (Friend Center Convocation Room)
Tool name: Cosi NoC: Open Source
Infrastructure for NoC Synthesis 2-2:30pm Break (Friend Center Downstairs Atrium)
On the Design of a Photonic Network-on-Chip (slides) Assaf Shacham, Keren Bergman and Luca P. Carloni (Columbia University)
NoC Communication Strategies using Time-to-Digital Conversion (slides) Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment and Alex Yakovlev (Newcastle University, UK)
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs Shuming Chen and Xiangyuan Liu (NUDT, China)
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures (slides) Ivan Miro Panades and Alain Greiner (UPMC, France) 4:10-4:30pm Break (Friend Center Upper Atrium)
Transaction-Based Communication-Centric Debug (slides) Kees Goossens, Bart Vermeulen (NXP), Remco van Steeden (U. Twente) and Martijn Bennebroek (Philips, NL)
The impact of higher communication layers on NoC supported MP-SoC (slides) Theodore Marescaux, Erik Brockmeyer (IMEC) and Henk Corporaal (TU Eindhoven, NL)
The Power of Priority: NoC based Distributed Cache Coherency (slides) Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar and Avinoam Kolodny (Technion, Israel)
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study (slides) Dominique Borrione, Amr Helmy, Laurence Pierre (TIMA, France) and Julien Schmaltz (Saarland University, Germany)
Access Regulation to Hot-Modules in Wormhole NoCs (slides) Isask'har Walter, Israel Cidon, Ran Ginosar and Avinoam Kolodny (Technion, Israel)
8:00-8:30am Breakfast (Friend Center Upper Atrium)
9:30-10am Break
Approaching Ideal NoC Latency with Pre-Configured Routes (slides) George Michelogiannakis, Dionisios Pnevmatikatos and Manolis Katevenis (ICS-FORTH, Crete, Greece)
A Power and Energy Exploration of Network-on-Chip Architectures (slides) Arnab Banerjee, Robert Mullins and Simon Moore (Cambridge, UK)
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing (slides) Terrence S.T. Mak, Pete Sedcole, Peter Y.K. Cheung, Wayne Luk (Imperial College, UK) and Kai-Pui Lam (TCU, Hong Kong)
Region-Based Routing. An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips (slides) Jose Flich, Andres Mejia, Pedro Lopez and Jose Duato (UPV, Spain)
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing (slides) Stephan Bourduas and Zeljlko Zilic (McGill U., Canada) 12:05-1pm Lunch Break (Kalluri Corner) 1-2pm Panel Session (Friend Center Auditorium) Proliferating the Use and Acceptance of NoC Benchmark Standards Organizer: Axel Jantsch (KTH, Sweden) Moderator: Ian Mackintosh (OCP-IP) (slides) Panelists: John Bainbridge (Silistix) (slides) Radu Marculescu (CMU) (slides) Timothy Pinkston (USC and NSF) (slides) Drew Wingard (Sonics) (slides)
An analytical approach for dimensioning mixed traffic networks (slides) Per Badlund and Axel Jantsch (KTH, Sweden)
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip (slides) Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand (CEA-LETI), Vincent Beroulle and Chantal Robach (INPG-LCIS, France)
A study of NoC Exit Strategies (slides) Mikael Millberg and Axel Jantsch (KTH, Sweden)
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation (slides) Rostislav Dobkin, Ran Ginosar and Israel Cidon (Technion, Israel)
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links (slides) Simon Ogg (U. Southampton, UK), Enrico Valli (U. Bologna, Italy), Crescenzo D'Alessandro, Alex Yakovlev, Bashir Al-Hashimi (U. Newcastle) and Luca Benini (U. Bologna, Itlay)
Thermal Impacts on NoC Interconnects (slides) Sheng Xu, Ibis Benito and Wayne Burleson (U. Massachusetts)
NOC-centric security of reconfigurable SoC (slides) Jean-Philippe Diguet, Guy Gogniat, Samuel Evain, Romain Vaslin and Emmanuel Juin (UBS/CNRS, France)
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases (slides) Andreas Hansson (Eindhoven U., NL) and Kees Goossens (NXP, NL)
Mesh of Tree: Unifying mesh and MFPGA for better device performances (slides) Zied Marrakchi, Hayder Mrabet, Christian Masson and Habib Mehrez (LIP6, France)
NoC-Based FPGA: Architecture and Routing (slides)
Roman Gindin, Israel Cidon and
Idit Keidar (Technion, Israel) 7pm Dinner Banquet (Prospect House) Reflections on 10 years as a commercial on-chipinterconnect provider (slides) Drew Wingard, Sonics
NOCS 2008 Alex Yakovlev, Newcastle University, UK
8:00-8:30am Breakfast (Friend Center Upper Atrium)
9:30-10am Break
NoC Design and Implementation in 65nm Technology (slides) Antonio Pullini (Torino), Federico Angiolini (Bologna), Paolo Meloni (Cagliari), David Atienza (EPFL), Srinivasan Murali (Stanford), Luigi Raffo (Cagliari), Giovanni De Micheli (EPFL) and Luca Benini (Bologna)
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance (slides) Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee and Simon Moore (Cambridge, UK)
ASC, a SystemC extension for Modeling Asynchronous Systems, and its application to an Asynchronous NoC (slides) Cedric Koch-Hofer, Marc Renaudin (TIMA), Vvain Thonnart and Pascal Vivet (CEA-LETI, France) 11:15-11:45am Break (Friend Center Upper Atrium)
Implementing DSP Algorithms with On-Chip Networks (slides) Xiang Wu (AMD), Tamer Ragheb, Yehia Massoud (Rice U.) and Adnan Aziz (UT Austin)
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network (slides) Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien and An-Yeu (Andy) Wu (NTU, Taiwan)
Fast, Accurate and Detailed NoC Simulations (slides) Pascal T. Wolkotte, Philip K.F. Holzenspies and Gerard J.M. Smit (U. Twente, NL)
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