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The 1st ACM/IEEE International Symposium on Networks-on-Chip ¡@
Title: Enabling Technology for On-Chip Interconnection Networks Speaker: Bill Dally, Bell Professor and Chair of CS, Stanford University Abstract: As we enter the era of many-core processors and complex SoCs, on-chip interconnection networks play a dominant role in determining the performance, power, and cost of a system. These networks are critically dependent on a number of underlying technologies: channel, buffer, and switch circuits, router microarchitecture, flow-control and routing methods, and network topology. Too often on-chip networks are built in a naiive manner using a ring or mesh topology and standard cell methodology. Compared to this approach, optimized circuits can reduce power by an order of magnitude and an optimized topology can give an additional factor of two to three in area and power efficiency. This talk will explore key enabling technologies for on-chip networks giving a number of examples and identifying opportunities for future research. Bio: Bill Dally is the Willard R. and Inez Kerr Bell Professor of Engineering and the Chairman of the Department of Computer Science at Stanford University. Bill and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Telephone Laboratories Bill contributed to the design of the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. While a Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. At Stanford University his group has developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations. Bill has worked with Cray Research and Intel to incorporate many of these innovations in commercial parallel computers, with Avici Systems to incorporate this technology into Internet routers, co-founded Velio Communications to commercialize high-speed signaling technology, and co-founded Stream Processors, Inc. to commercialize stream processor technology. He is a Fellow of the IEEE, a Fellow of the ACM and has received numerous honors including the IEEE Seymour Cray Award and the ACM Maurice Wilkes award. He is chairman of Stream Processors and on the board of directors of Portal Player. He currently leads projects on high-speed signaling, computer architecture, network architecture, and programming systems. He has published over 170 papers in these areas and is an author of the textbooks, Digital Systems Engineering and Principles and Practices of Interconnection Networks. . ¡@ |
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