CALL FOR PAPERS


May 7-9, 2007

Princeton University, New Jersey

GENERAL CO-CHAIRS
Eby Friedman, Rochester, USA
Wayne Wolf, Princeton, USA

 

PROGRAM COMMITTEE CO-CHAIRS
Avi Kolodny, Technion , Israel
Li-Shiuan Peh, Princeton, USA

 

LOCAL ARRANGEMENTS CHAIR

Luca Carloni, Columbia University, USA

 

PUBLICATIONS CHAIR

Tor Aamodt, UBC, Canada                            

PUBLICITY CHAIRS

Srinivasan Murali, Stanford, USA

Li Shang, Queen’s U., Canada

 

REGISTRATION CHAIR

Karam Chatha, Arizona State U., USA

 

FINANCE CHAIR

Karam Chatha, Arizona State U., USA

 

WEB CHAIR

Amit Kumar, Princeton, USA

 

STEERING COMMITTEE
Alex Yakovlev, NCL, United Kingdom

Avi Kolodny, Technion , Israel

Axel Jantsch, KTH,  Sweden

Eby Friedman, U. Rochester, USA

Giovanni de Micheli, EPFL, Switzerland

Kees Goossens, Philips, Netherlands

Li-Shiuan Peh, Princeton, USA

Pol Marchal, IMEC, Belgium

Ran Ginosar, Technion, Israel

Wayne Wolf, Princeton, USA

 

PROGRAM COMMITTEE

Adam Donlin, Xilinx, USA                                     

Alain Greiner, LIP6, Paris, France

Alberto Sangiovanni-Vincentelli, Berkeley, USA

Alex Yakovlev, U. Newcastle, UK

Anand Raghunathan, NEC C&C Labs, USA

Andre Ivanov, UBC, Canada

Avi Kolodny, Technion, Israel

Axel Jantsch, KTH, Sweden

Bill Lin, UCSD, USA

Brian Towles, D E Shaw, USA

Chita Das, Penn State, USA

Davide Bertozzi, U. of FERRARA, Italy

Drew Wingard, Sonics, USA

Eby Friedman, U. Rochester, USA

Frederic Petrot, TIMA, Grenoble, France

Giovanni de Micheli, EPFL, Switzerland

Hoi-Jun Yoo, KAIST, Korea

Jari Nurmi, Tampere U. Tech., Finland

Jens Sparsoe, DTU, Denmark

John Bainbridge, Silistix, UK

Kees Goossens, Philips Research, Netherlands

Li Shang, Queen’s U. Canada

Li-Shiuan Peh, Princeton, USA

Luca Benini, Bologna, Italy

Luca Carloni, Columbia, USA

Matthias Blumrich, IBM Research, USA

Partha Kundu, Intel, USA

Petru Eles, Linkoping U., Sweden

Philippe Martin, Arteris, France

Pol Marchal, IMEC, Belgium

Radu Marculescu, CMU, USA

Ran Ginosar, Technion, Israel

Riccardo Locatelli, STM, France

Robert Mullins, Cambridge, UK

Shashi Kumar, Jonkoping U., Sweden

Shinobu Fujita, Toshiba, Japan

Simon Moore, Cambridge, UK

Steve Furber, Manchester, UK

Tapani Ahonen, Tampere, Finland

Timothy Pinkston, NSF and USC, USA

Wayne Wolf, Princeton, USA

 

Network-on-Chip (NoC) is an emerging paradigm using packet-switched networks for communications within large VLSI systems on-chip. NoCs are poised to provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures such as busses and dedicated signal wires. The NOC symposium brings together academic and industrial researchers and developers addressing issues of NoC-based systems at all levels, from the physical on-chip link level through the network level, and ranging up to system architecture and application software.

 

TECHNICAL SCOPE

Papers are solicited which address new and previously unpublished results in the following areas.  Proposals for tutorial papers and panel sessions are also invited. A special section related to the theme of the conference in the IEEE Transactions on VLSI Systems.

 

  • Network architecture (topology, routing, arbitration,…)

  • Power and energy issues in NoC

  • NoC case studies, application-specific NoC design

  • Timing, synchronous / asynchronous communication

  • NoC reliability issues

  • O/S support for NoC

  • Metrics and benchmarks for NoCs

  • NoC Network interface issues

  • Modeling, simulation, and synthesis of NoCs

  • Network-on-chip design methodologies

  • NoC Quality of Service

  • NoC support for CMP / MPSoC

  • NoC support for memory access

  • NoCs for  FPGAs and structured ASICs

  • Programming models

  • Mapping of applications onto NoCs

  • Novel interconnect links / switches / routers

  • Signaling and circuit design for NoC links

  • Physical design of interconnect and NoC

  • NoC design tools

 

PAPER SUBMISSION

Electronic paper submission requires a full paper, up to 10 double-column IEEE format pages, including figures and references.

 

 

DEADLINE FOR PAPER SUBMISSION:  December 1, 2006

(Automatic extension to December 10, 2006)

NOTIFICATION OF PAPER ACCEPTANCE:  February 5, 2007

FINAL CAMERA-READY PAPERS DUE:  March 4, 2007

Please visit the conference web site for paper submission, registration, and current conference information.

 

Conference Web Site: http://nocsymposium.org

Sponsored by the IEEE Circuits and Systems Society, Council for EDA, ACM Special Interest Group on Computer Architecture (SIGARCH), ACM Special Interest Group on Embedded Systems (SIGBED)